Since traditional two dimensional (2D) planar architecture of interconnects in semiconductor devices inevitably imposes restrictions on miniaturization, new interconnection and packaging technologies need to be developed to keep on track with the continuously scaling of electronic systems. Three dimensional (3D) integration is an interesting solution since it allows for reduction of the system size, both in area and volume. Furthermore, it improves performance since 3D interconnects are shorter than in a 2D configuration, enabling a higher operation speed and smaller power consumption. A third advantage is the possibility of hetero-integration, the “seamless” mixing of different microelectronic technologies at wafer level. Different technology solutions are available for creating 3D interconnects. The highest interconnect density can be obtained with the 3D-stacked IC approach (3D-SIC). In this concept a deep via is etched through the Pre Metal Dielectric (PMD) into the Si after the front end of line (FEOL) processing. Only after metalizing the vias the back end of line (BEOL) processing is done. This puts minimal impact on CMOS wafer design because of the small exclusion area on the FEOL, the absence of impact on the BEOL wiring and the small number of necessary additional process steps.
Another promising application of using deep vias in stacked semiconductor structures is the coupling of stacked semiconductor structures or components for Micro-Electro-Mechanical Systems (MEMS) with each other by means of deep vias filled with conductive material.
The applications mentioned above require the etching of high-aspect ratio deep vias in a patterned thick semiconductor structure or a substrate and fill it with a conductive material. To ensure a reliable electrical connection between stacked semiconductor wafers or between elements of the devices in MEMS applications, a passivation layer, a barrier layer, and a seed conductive layer, such as a copper layer for electroplating needs to be deposited onto the sidewalls of the deep via. Said passivation and/or barrier layer must be smooth and uniform to allow the conductive material to uniformly fill the opening.
However, etching of said deep vias in the silicon substrate is not straightforward since standard etching procedures known in prior art for etching openings (vias) in a semiconductor substrate result in substantial undercut of the hardmask which is detrimental for the deposition of a conformal TaN barrier layer afterwards. The deep vias for connecting stacked 3D interconnects typically have an aspect ratio up to 10:1 which makes it impossible to use standard etching procedures.
One method available in the prior art to avoid the hardmask undercut is using a polymerizing etch process. During this process, a polymer layer is deposited on the sidewalls of the etched silicon substrate to block the lateral component of etching, resulting in a reduction of a hard mask undercut. However, this method employs ions with high energy, which may cause damage to a semiconductor structure due to an excessive ion bombardment. Further, the residuals of the polymer layer left on the sidewalls of the etched structure may cause a problem for a subsequent wet cleaning process. More specifically, the residuals of the polymer layer left on the sidewalls may impact the device's performance leading to a device reliability problem.
Another method that attempts to overcome the barrier layer non-uniformity caused by the oxide hardmask undercut uses the atomic layer deposition (ALD) process to deposit a uniform barrier layer. Since, during the ALD process, a material is deposited sequentially one atomic layer after another, this method is very time-consuming and expensive.
In US2005/0274691 a portion of the opening in the silicon substrate is etched generating a hard mask undercut. Then, the hard mask layer is trim-etched to remove the hard mask undercut. Next, the portion of the opening in the substrate is etched for a second time, generating a hard mask undercut for a second time. Trim-etching the hard mask followed by etching the portion of the opening in the substrate is continuously repeated until a predetermined depth of the opening in the substrate is achieved. This method is rather complicated and rather difficult to obtain smooth sidewalls and to have control on the CD of the via.
Thus, the prior art proposes several solutions for eliminating undercut but all of them do have serious drawbacks and shortcomings. The prior art does never provide a solution that eliminates the undercut in the silicon substrate without substantially altering the standard etch plasma and process used to etch a silicon substrate.